1. Field of the Invention
This invention relates to a picture encoding apparatus used for reducing the bit rate of a picture signal for longterm recording, low rate transmission and other purposes, and to a picture decoding apparatus for decoding a signal encoded by the picture encoding apparatus.
2. Description of the Prior Art
As a conventional picture encoding apparatus, for example, a motion compensation inter-frame/intra-frame encoding apparatus is disclosed in Japanese Laid-Open Patent Application No. 4-68989.
This picture encoding apparatus compares through a motion vector detector a decoded picture signal of a preceding picture as a reference picture and an input picture to detect such motions as panning (parallel movement) and zooming (enlargement and reduction). Then, a motion compensating circuit effects parallel movement, enlargement and reduction the whole of the reference picture so as to cancel the detected panning and/or zooming to generate a compensated reference picture whereby the pixel value difference between the input picture and the compensated reference picture is made small. In this case, a differential signal for each pixel between the input picture and the compensated reference picture is calculated by an inter-frame differential calculator. An inter-frame/intra-frame selector selects the differential signal or the input picture signal depending on the magnitude of the differential signal obtained by the inter-frame differential calculator and outputs the selected signal to an encoder for encoding. Furthermore, the encoded signal is simultaneously decoded by a decoder and stored in a frame memory to be used as the reference picture for encoding of the next picture.
With the structure as shown above, however, the decoded signal of the preceding picture is used as the reference picture when the present picture is encoded. As a result, the present signal cannot be encoded if the preceding picture is not encoded and decoded. Therefore, it is impossible to encode plural pictures in parallel, so that the use high speed operable components is necessary, making hardware implementation difficult.